Arithmetic Built-In Self-Test for Embedded Systems by Janusz Rajski PDF

By Janusz Rajski

ISBN-10: 3540404481

ISBN-13: 9783540404484

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Additional info for Arithmetic Built-In Self-Test for Embedded Systems

Sample text

Deterministic patterns are generated by loading the LFSR with an 5-bit seed (s < k) and applying enough cycles to fill the scan chain. The seed specifies the first s positions of the LFSR, while the other k — s positions are assumed to be reset. Hence, loading the seed can be performed by resetting the LFSR and shifting the s-bit seed serially, starting with its least significant bit. 3. 11: Decompressor hardware. for each pattern, and can be overwritten between the applications of patterns. Consequently, the LFSR can be implemented by using scan flip-flops.

5k. Other probabilities can be also obtained by using OR gates and inverters. It is important to note that the stuck-at-1 fault at the output z of the circuit shown in Fig. 10a requires different weights than those for y s-a-0, as now each input should receive a 1 with a probability of 1 — (31/32) = 1/32. Unfortunately, there is no common weight set for both faults, and therefore two different weights have to be stored for each circuit input. In general, a circuit may require several sets of weights, and, for each weight set, a number of random patterns have to be applied.

In its simplest form, as introduced by HewlettPackard [62], the LFSR is modified to accept an external input in order to act as a polynomial divider, as shown in Fig. 14a. An alternative implementation (called type 2 LFSR) is shown in Fig. 14b. The input sequence, represented by a polynomial, is divided by the characteristic polynomial of the LFSR. As 34 1. Built-in Self-Test the division proceeds, the quotient sequence appears at the output of the LFSR and the remainder is kept in the LFSR. Note that type 1 LFSRs do not always produce the correct remainder.

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Arithmetic Built-In Self-Test for Embedded Systems by Janusz Rajski


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